Senior SOC/ASIC DFT Engineer

- Bachelors degree in electrical engineering, computer engineering, or physics - Over 5 years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing - Masters or PhD in electrical engineering, computer engineering, physics, or a related field (preferred) - Significant experience in post-silicon bringup, silicon debugging, failure analysis, and yield improvement on complex SoCs or ASICs - Hands-on experience with Automated Test Equipment (ATE) platforms such as Teradyne or Advantest for high-volume manufacturing testing and debugging - Collaboration experience with cross-functional teams including design, verification, and manufacturing to meet production DFT requirements using Siemens Tessent workflows - Knowledge of industry standards for testability like IEEE 1500 and 1687, along with low-power DFT techniques using Siemens Tessent - Experience with In-System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board-level diagnostics, preferably utilizing Siemens Tessent tools - Practical experience with Tessent Streaming Scan Network - Knowledge of cell-aware fault models in ATPG - Strong problem-solving capabilities, proficient in analyzing complex test failures and executing corrective measures - Excellent communication skills for documenting test strategies, reporting findings, and engaging with stakeholders - Ability to thrive in a dynamic environment, managing multiple projects and adapting to evolving technology nodes (e.g., 7nm and below) - Willingness to work extended hours and weekends as necessary to meet critical deadlines