Senior DDR Verification Engineer

- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and a minimum of 1 year of technical engineering experience - Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and at least 4 years of technical engineering experience - Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 5 or more years of technical engineering experience - 7+ years of related technical engineering experience or an equivalent combination of education and experience - 5+ years of experience in pre-silicon subsystem or IP verification - 3+ years of experience specifically in verifying DDR subsystems - Proven ability to verify memory controllers, DDR PHY, and promote integration verification of memory controller IP with DDR PHY and EDA sourced DIMM Verification IP - Solid understanding of JEDEC specifications including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and error handling - Experience across the product cycle from definition to silicon, including test planning, developing tests, debugging issues, and signing off on coverage - Familiarity with creating, managing, or integrating test benches, checkers, and stimulus using UVM, System Verilog Test Bench, and Python for post-processing - Proficiency in scripting/software development using standard languages like Python - Experience leveraging generative AI in everyday tasks