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Jobot jobs

Full-Chip Timing Engineer

$185,000 - 235,000
Jobot
Pacific Coast Highway 3101, San Jose
$185,000 - 235,000
Company Size icon
Company Size
1k-5k
Company Type icon
Company Type
Services
Exp Level icon
Exp Level
Lead
Job Type icon
Job Type
Full-Time
Language icon
Language
English
Visa sponsorship icon
Visa sponsorship
No

Requirements

Must:
- Over 8 years of experience in the semiconductor industry - Proven track record in full-chip static timing analysis and signoff closure - Proficient in using PrimeTime (knowledge of Tempus is advantageous) - Experience with advanced technology nodes - Strong grasp of clock tree synthesis (CTS), setup and hold analysis, OCV/AOCV, and crosstalk - Effective scripting skills in Tcl (Python is a plus) - Experience in facilitating successful tapeouts

Responsibilities

- Lead full-chip static timing analysis from synthesis to signoff - Drive timing closure within multi-mode, multi-corner (MMMC) environments - Conduct thorough analysis using PrimeTime or a similar tool - Identify and execute ECO timing fixes - Collaborate with Physical Design, CTS, Synthesis, and Architecture teams - Support advanced-node tapeouts (preferably 7nm/5nm and below) - Contribute to enhancements in timing methodology and flows

Description


We are a dynamic semiconductor design firm focused on advanced ASIC and SoC development, prioritizing technical excellence, rapid execution, and a strong ownership culture. As we expand our engineering team in the Bay Area, we invite passionate individuals to join us and tackle the complexities of high-performance silicon solutions. Our culture emphasizes collaborative work with a competitive compensation package, providing opportunities to influence methodologies and achieve real impact in the design and signoff processes.
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