Mid-level design verification engineer

- Collaborate with cross-functional teams to ensure alignment in design verification processes - Implement verification strategies for RISC-V architecture projects - Utilize VC Formal DPV App for confirming arithmetic conformance of RTL to C/C++ models - Analyze and verify designs of L3 cache coherent systems with AXI and CHI interfaces - Write and maintain efficient C/C++ code for simulation tasks - Use Synopsys tools for verification workflows - Develop and execute Python-based simulations - Conduct formal verification to ensure design integrity - Oversee SOC system integration, ensuring successful booting of Linux OS - Execute Gate Level Simulations for verification purposes - Apply low power design techniques to enhance project efficiency